Programmable Logic

Programmable Logic Devices I Have Used

Introduction

Over the past 40+ years I have designed several projects that used programmable logic in order to reduce the number of ICs required on a board.

This web page only describes those of my projects that were actually built (even if not completely finished). However, over the years I also started designing various other projects that incorporated programmable logic, which were never (or at least not yet) built.

PAL16R8A and PAL16L8A

The RAM-512 board for the ST-2900, designed and built in 1985, uses one PAL16R8A-2 and 3 identically programmed PAL16L8A-4 chips. The logic equations are shown in the RAM-512 user manual, and you can find the device data sheet for them here.

Each PAL16L8A-4 chip implements a 3-channel multiplexer, with each channel having 3 inputs and 2 simultaneous outputs. The outputs connect to the address lines of the even and odd DRAM banks, allowing one bank to be refreshed in the same bus cycle as the other bank has data read from or written to it. Implementing this logic with standard 74LSxx parts would have required too many chips, so would not have fit into the desired board size.

I used PALASM running on a borrowed IBM PC compatible computer (since I didn't yet own one) to design the logic for these PAL chips, and had them programmed by the distributor, who was R.A.E. Industrial Electronics (see History section) in Burnaby BC Canada.

These were the very first programmable logic chips that I used in any of my projects.

PAL20L10

In 1986 I started designing a new floppy disk controller cartridge for the Radio Shack Color Computer (CoCo). The DMC ("No Halt" Dual Mode Controller), and its later PAL-4 daughterboard, used one 24-pin PAL20L10 (1.44MB .pdf) chip in order to reduce the number of ICs so they would all fit onto a standard CoCo cartridge size board.

However, this PAL was very power hungry, which was a major reason why my cartridge drew more current than the CoCo's power supply was supposed to deliver to its expansion slot.

I again used PALASM to design the logic for this PAL chip.

Lattice ispLSI 1032 and 1016

Probably in 1992 or 1993, while I was working for BC Hydro, one of the engineers in my department designed a sophisticated system to measure partial discharge in hydroelectric generator windings. Besides using some very fast ECL comparators and logic chips, he also used many 74HCxx chips in his board design. By this time I was aware of the new Lattice ispLSI 1032 (622KB .pdf) CPLD that was electrically erasable and in-system programmable. I convinced them that I could replace over two dozen 74HCxx chips with one 84-pin CPLD, greatly simplifying the board and its layout, as well as converting most of the asynchronous logic into synchronous logic. They then let me design the logic equations in this chip.

Lattice supplied easy-to-use design software (called pDS) that ran under Microsoft Windows, except that moving equations from one logic block to another was rather tedious. So I wrote a pre-processor program (in QuickBASIC?) that made assigning product terms to specific logic blocks much easier. Logic equations were written using a syntax similar to ABEL.

An engineering student, working for us during his co-op term, designed another board for this system that used the smaller 44-pin ispLSI 1016 CPLD. Later I re-wrote his logic equations to use synchronous logic instead of asynchronous.

In November 1979, during commissioning at the BC Hydro Peace Canyon Project, a generator suffered significant rotor-stator contact damage. In order to diagnose the cause of this contact, BC Hydro needed dynamic air gap measurements, so they invented and patented (US 4,766,323) a method to measure the air gap between the rotor and stator of a hydroelectric generator while it was running, using retro-reflective optical triangulation. It was developed into their Air Gap Monitor (AGM), as described in this IEEE paper. But the electronics in the AGM that converted the pulses received from the sensors into gap values was rather expensive and had limitations. For example, since the pairs of pulses from each of the two optical paths in a sensor were merged into one signal, at certain gaps they overlapped and couldn't be measured.

In late 1993 I figured out a better method to process the pulses from the air gap sensors, that allowed one board to process up to 8 sensors (16 optical paths or channels), rather than needing a separate board for each sensor or channel. It also increased the range of operation, and had many other improvements. The technique involved a 16-bit counter that incremented at the 16 MHz pulse sampling frequency, and whenever any input signal changed its level, a record containing the counter value and the levels of all input signals was written to a FIFO. Since the counter would wrap around to zero 244 times per second, a record was also written to the FIFO every time the counter wrapped. This allowed the software on the host computer to extend the counter size to whatever was required to eliminate wrapping during one session or in one file. The FIFO was required because at times the host computer couldn't process the records as fast as they were being generated, even though it could catch up during quieter periods.

I designed and built a simplified proof-of-concept board (DTD = Digital Timing Demo) with only four input channels, that used the ispLSI 1016 and two 512x9 FIFO chips -- see picture. A former co-worker did the PCB layout for me. The DTD board could be plugged into either an 8-bit ISA bus (IBM PC) connector, or a PC/104 connector. It sampled the pulses at 12 MHz and used a 12-bit counter. One option was to use Gray code for the 12-bit count instead of binary. (Several years later I even used this board, plus a program written in QuickBASIC or QBASIC, as a logic analyzer to debug problems for other clients.)

According to my notes I also used Lattice CPLDs in other projects for BC Hydro: an ispLSI 1016 in the AB71-IRIGB module that plugged into an Allen-Bradley 1771 PLC chassis, and an ispLSI 1032 in a support board for their Harmonics Filter.

Altera FLEX 10K10

In 1997 I became interested in the Altera FLEX 10K, which seemed to be a hybrid, having features of both CPLDs and FPGAs. It contained CMOS SRAM-based logic elements with 4-input lookup tables (LUT) like an FPGA, but they were grouped into Logic Array Blocks (LAB) like a CPLD. It also had Embedded Array Blocks (EAB) that could implement RAM, ROM, dual-port RAM, or FIFOs, like an FPGA. But instead of segmented routing paths that other FPGAs typically used, the FLEX 10K had lots of long horizontal and vertical routing channels.

I wanted to use the FLEX 10K10 (with 576 logic elements) to implement two projects. The first one was to be an improved DTD board, that handled many more air gap channels, and used the on-chip EABs as FIFOs, eliminating the expensive external chips. I don't remember finishing this design.

The other project was to try and implement a microprocessor core emulating most of the Motorola 6800 µP. I used AHDL (Altera Hardware Description Language) to create the design. I created most of the data path (except for the condition code equations), which used approximately half of the logic elements. Could I have fit all the control logic into the remaining resources? Maybe not, but I put the project aside before trying to finish it. It was built on an 8-bit ISA bus prototyping board -- see picture above. I don't remember how I configured it, as my board does not have an EPC1 or similar OTP configuration ROM on it. Did I build a clone of the Altera ByteBlaster programmer that plugged into my PC's parallel printer port?

Lattice ispMACH 4064V

In January 2016 I started designing a device to capture the raw flux signals from a floppy disk drive, in order to image my hundreds of old floppy disks. The final design, which I called the Universal Floppy Disk Reader (UFDR), used a TI ADS930 8-bit 30 MS/s pipelined ADC to capture the analog waveform, a Lattice ispMACH 4064V 44-pin CPLD to capture the digital read signal from the drive and merge 8 analog and 8 digital samples (all taken at 15 MS/s) into one 10-byte packet. These packets were written into a 4Kx9 synchronous FIFO, which in turn sent them to the host PC via an FTDI FT232H USB-FIFO. The logic equations were written in ABEL and processed with the ispLEVER Classic CPLD design software.

Purchased Boards

Although I didn't design or build these, I have also purchased and used an off-the-shelf Lattice ispMACH 4256V Breakout Board, as well as the WebFPGA ShastaPlus board that uses the Lattice iCE40UP5K FPGA.

Home Contact Site map